In today's electrical devices and equipment, certain subsystems may require a low noise power supply for proper operation. One example of a subsystem which may require a low noise power supply for proper operation is the Radio Frequency (RF) subsystem associated with communication equipment for transmitting and receiving RF signals. An RF subsystem is often powered by a low noise power supply, as significant noise associated with the power supply may interfere with RF operation. As an example, significant noise from the power supply may be coupled or modulated onto the transmitted RF signal, potentially rendering it unrecoverable by an RF receiver.
Usually, on the system level, such communication equipment is often powered by a single system power supply providing multiple differing voltage rails to the various subsystems. In addition, the subsystems may incorporate a multiplicity of differing voltage rails for supplying power to the associated functional blocks. The subsystems, and functional blocks associated with the subsystems, produce noise with the potential for the noise being coupled back onto the system power supply. Furthermore, the coupling of system noise associated with the system power supply may render the system power supply as “noisy.” As such, the noise coupling associated with the system power supply may require rejection for providing adequate clean power to electrical subsystems.
A power switch is commonly used to connect and disconnect a system power supply from a subsystem (e.g. RF subsystem). Furthermore, the multiple voltage rails used to power the functional blocks within the subsystem may be generated by internal voltage regulators incorporating a noise rejection function. Since there may be multiple voltage rails in the subsystem, a multiplicity of voltage regulators may be deployed for performing noise rejection. The deployment of multiple voltage regulators increases design complexity as well as subsystem cost and system cost.
Power switches deployed may often be configured as “high-side” type connecting and disconnecting the load associated with a power source, as opposed to “low-side” type, which may be configured for performing connecting and disconnecting associated with ground potential.
A typical high-side power switch employs a “Pass Element” connecting (i.e. ON) and disconnecting (i.e. OFF) a load associated with a system power supply. Furthermore, a typical high-side power switch employs a “Gate Drive and Level Shift (GDLS)” circuit for controlling the ON/OFF condition for the pass element. The GDLS is often controlled by an enable input for configuring the ON/OFF condition.
Typically, the pass element of a high-side power supply switch is a PNP transistor, or a P-channel MOSFET. Since a P-channel MOSFET is often used in today's semiconductor-based high-side power switches as the pass element, a P-channel MOSFET will be used to illustrate the circuit implementations for the pass element described in the following paragraphs with reference to the figures.
FIG. 1 presents an illustration of a conventional high-side power switch.
A high-side power switch 100 includes an input voltage signal 102, an input enable signal 104, a ground signal 106, an output voltage signal 108, a P-channel MOSFET 110 and a GDLS portion 112.
High-side power switch 100 may operate as a mechanism for connecting and disconnecting a load (not shown) to a system power source.
Input voltage signal 102 received from an external source, may operate to supply a voltage signal. Input enable signal 104 received from an external source, may operate to supply a signal for enabling or disabling high-side power switch 100. Ground signal 106 may operate to provide a signal supplying a ground potential. Output voltage signal 108 may operate to supply a voltage signal external to high-side power switch 100.
P-channel MOSFET 110 may operate as a pass element for connecting and disconnecting a load to a system power supply.
GDLS portion 112 may operate to control the on/off condition for P-channel MOSFET 110.
GDLS portion 112 includes an N-channel MOSFET 114, a pull-down resistor 116 and a pull-up resistor 118.
N-channel MOSFET 114 may operate to provide configuration control for P-channel MOSFET 110.
Pull-down resistor 116 may operate to provide ground potential to the gate terminal of N-channel MOSFET 114 when the signal source for the gate of N-channel MOSFET 114 delivers high impedance. Furthermore, providing ground potential to the gate terminal of N-channel MOSFET 114 may operate to configure N-channel MOSFET 114 for an open condition.
Pull-up resistor 118 may be configured such that N-channel MOSFET 114 may be driven to saturation resulting in an operational condition (i.e. closed/on) for P-channel MOSFET 110.
Source of P-channel MOSFET 110 and the first terminal of pull-up resistor 118 may receive input voltage signal 102. Gate terminal of P-channel MOSFET 110 may receive a signal 120. Furthermore, signal 120 may be connected to the first terminal of pull-up resistor 118 and the drain terminal of N-channel MOSFET 114. Output voltage signal 108 may be sourced by the drain terminal of P-channel MOSFET 110. The gate terminal of N-channel MOSFET 114 and the first terminal of pull-down resistor 116 may receive input enable signal 104. The source terminal for N-channel MOSFET 114 and the second terminal of pull-down resistor 116 may receive ground signal 106.
GDLS portion 112 may be constructed in a manner where presentation of logic HIGH via input enable signal 104 results in driving the voltage to the gate terminal of P-channel MOSFET 110, denoted as VG—110, to a lower voltage than the voltage applied to the source terminal of P-channel MOSFET 110, denoted as VS—110. Furthermore, the voltage differential between VS—110 and VG—110, denoted as VSG—110, should be a voltage greater than the threshold voltage for P-channel MOSFET 110, where the threshold voltage for P-channel MOSFET 110 may be denoted as VTH—110. VTH—110 may be considered as the voltage for configuring P-channel MOSFET 110 for a condition of operating (i.e. closed/on). The operation as described with reference to P-channel MOSFET 110 for this paragraph may be presented by Equation 1A as shown below:VSG—110=VS—110−VG—110>VTH—110  (1A)
Typically, VG—110 may be driven to a voltage near ground potential in order to ensure the condition as presented by Equation 1A may be satisfied, and further ensure that P-channel MOSFET 110 operates on the boundary between its saturation region and its non-saturation region (e.g. voltage differential between P-channel MOSFET 110 source terminal and drain terminal=VSD—110=VS—110−VD—110=VSG—110−VTH—110) to maximize the current supplied by P-channel MOSFET 110 while minimizing VSD—110.
For a condition of input enable signal 104 configured for logic LOW or high impedance, GDLS portion 112 may operate to drive VG—110 to a voltage level greater than the differential of VS—100 and VTH—110, as presented Equation 1B as shown below:VSG—110=VS—110−VG—110<VTH—110  (1B)
Typically, VG—110 may be driven to a voltage approximate to VS—110 in order to ensure the conditions as presented by Equation 1B may be satisfied (i.e. P-channel MOSFET 110 configured for condition of non-operating/off).
The operational/non-operational state (i.e. open/closed or on/off) for N-channel MOSFET 114 may be controlled via input enable signal 104. For presentation of a logic HIGH to input enable signal 104, N-channel MOSFET 114 may be considered as configured for a closed (i.e., on) condition. The value of pull-up resistor 118 may be chosen such that N-channel MOSFET 114 may be driven to saturation. Furthermore, VG—110 may be configured for a voltage slightly greater than ground potential, resulting in configuration of P-channel MOSFET 110 for a closed/on condition. For presentation of a logic LOW (e.g. ground potential) to input enable signal 104, N-channel MOSFET 114 may be considered as configured for an open (i.e., off) condition. Furthermore, VG—110 may be pulled up to the voltage level of VS—110 by pull-up resistor 118, resulting in the configuration of P-channel MOSFET 110 for a condition of open (i.e., off). For high impedance applied to input enable signal 104, the gate terminal of N-channel MOSFET 114 may be pulled to ground potential by pull-down resistor 116. Furthermore, N-channel MOSFET 114 may be configured for a condition of open (i.e., off). Furthermore, VG—110 of P-channel MOSFET 110 may be pulled up to the voltage level of VS—110 by pull-up resistor 118, resulting in configuration of P-channel MOSFET 110 for a condition of open (i.e., off).
FIG. 2 presents an illustration of a conventional high-side power switch.
A high-side power switch 200 includes an input voltage signal 202, an input enable signal 204, a ground signal 206, an output voltage signal 208, a P-channel MOSFET 210 and a GDLS portion 212.
High-side power switch 200 may operate as a mechanism for connecting and disconnecting a load to a system power source.
Input voltage signal 202 received from an external source, may operate to supply a voltage signal. Input enable signal 204 received from an external source, may operate to supply a signal for enabling or disabling high-side power switch 200. Ground signal 206 may operate to provide a signal supplying a ground potential. Output voltage signal 208 may operate to supply a voltage signal external to high-side power switch 200.
P-channel MOSFET 210 may operate as a pass element for connecting and disconnecting a load to a system power supply.
GDLS portion 212 may operate to control the on/off condition for P-channel MOSFET 210.
GDLS portion 212 includes an N-channel MOSFET 214, a pull-down resistor 216 and a P-channel MOSFET 218.
N-channel MOSFET 214 and P-channel MOSFET 218 may operate to provide configuration control for P-channel MOSFET 210.
When the signal source for the gate of N-channel MOSFET 214 and P-channel MOSFET 218 delivers high impedance, pull-down resistor 216 may operate to provide ground potential to the gate terminal of N-channel MOSFET 214 and the gate terminal of P-channel MOSFET 218. Furthermore, providing ground potential to the gate terminal of N-channel MOSFET 214 may operate to configure N-channel MOSFET 214 for an open condition. Furthermore, providing ground potential to the gate terminal of P-channel MOSFET 218 may operate to configure P-channel MOSFET 218 for a closed and saturation condition.
The source terminal of P-channel MOSFET 210 and the source terminal of P-channel MOSFET 218 may receive input voltage signal 202. Gate terminal of P-channel MOSFET 210 may receive a signal 220. Furthermore, signal 220 may be connected to the drain terminal of P-channel MOSFET 218 and the drain terminal of N-channel MOSFET 214. Output voltage signal 208 may be sourced by the drain terminal of P-channel MOSFET 210. The gate terminal of N-channel MOSFET 214, the gate terminal of P-channel MOSFET 218 and the first terminal of pull-down resistor 216 may receive input enable signal 204. The source terminal for N-channel MOSFET 214 and the second terminal of pull-down resistor 216 may receive ground signal 206.
For a logic HIGH presented to input enable signal 204, N-channel MOSFET 214 may be driven to operation in the saturation region and as a result configured for a condition of closed. Furthermore, P-channel MOSFET 218 may be configured for a condition of open. Furthermore, the gate terminal of P-channel MOSFET 210 may be configured for a voltage potential of ground (or near ground), resulting in a configuration for P-channel MOSFET 210 of closed (i.e. on). For a logic LOW presented to input enable signal 204, N-channel MOSFET 214 may be configured for a condition of open. Furthermore, P-channel MOSFET 218 may be configured for operation in the saturation region and considered as a closed condition. Furthermore, the voltage for the gate terminal of P-channel MOSFET 210 may be configured for a voltage level associated with the source voltage of P-channel MOSFET 210, resulting in a configuration of an open (i.e. off) condition for P-channel MOSFET 210. For high impedance presented to input enable signal 204, input enable signal 204 may be pulled down to ground potential via pull-down resistor 216, or a similar condition as a logic LOW presented to input enable signal 204. Furthermore, N-channel MOSFET 214 may be configured for an open condition. Furthermore, P-channel MOSFET 218 may be configured for saturation resulting in a closed condition. Furthermore, the voltage of the gate terminal for P-channel MOSFET 210 may be driven to the voltage of the source terminal of P-channel MOSFET 210 (or near), resulting in a configuration of open (or off) for P-channel MOSFET 210.
The high-side power switches as described with reference to FIG. 1 and FIG. 2 may operate adequately for connecting and disconnecting a load from a system power supply.
Details associated with Power Supply Rejection Ratio (PSRR) may be introduced in order to further discuss noise rejection associated with the switches as described with reference to FIGS. 1-2. The ability for the high-side power switches to reject noise associated with a system power supply may be calculated via PSRR. The high-side power switches as discussed with reference to FIGS. 1-2 may be considered essentially as a unity gain voltage amplifier without a feed back loop. As a result, the PSRR for the high-side power switches of FIGS. 1-2 may be presented by Equation 2A as shown below:PSRR=ΔVDD/ΔVOUT=ΔVIN/ΔVOUT  (2A)
PSRR may also be expressed in decibels as presented by Equation 2B as shown below:PSRR=20 log(ΔVIN/ΔVOUT)  (2B)
From Equation 2A and Equation 2B for the high-side power switches of FIG. 1-2, the voltage gain may considered as approximately unity with feedback loop not configured. Furthermore, the PSRR may be unity (or 0 dB) and may be interpreted as not providing noise or ripple rejection.
In view of the foregoing, there is a need for improved techniques for providing noise rejection techniques for power supplies.
Unless otherwise indicated illustrations in the figures are not necessarily drawn to scale.